1. Technical Field
The embodiments herein generally relate to modulation, demodulation, and trans-modulation of an input signal, and, more particularly, to a software defined radio subsystem that is capable of supporting modulation, demodulation and trans-modulation for multiple analog and digital communication standards.
2. Description of the Related Art
Typical demodulator solutions today which cater to communication standards such as Digital TV (DTV) standards and/or Analog TV (ATV) standards consist of separate pieces of digital signal processing hardware blocks which are standard specific. With the proliferation of medium specific and region specific communication standards, supporting all standards on a single chassis is becoming necessary to reduce the diversity cost of maintaining different production lines for different standards. If one were to make a system solution using different region and medium specific demodulators, the bill of materials cost would be very high for end customers. The process of developing a single chip to address such diversity using system on chip integration of signal processing hardware blocks leads to very large silicon area thus leading to prohibitively higher costs.
In addition, supporting such a multitude of standards using a single programmable processor would necessitate operating it at an extremely high frequency (e.g., several tens of Gigahertz) which would consume extremely high power thus making it unviable for consumer usage. Hence there is a need to develop a solution which is area inexpensive, that consumes lower power, and that also caters to a multitude of both digital and analog communication standards. Also, RF tuners which interface with various TV demodulators operate at various intermediate frequencies (IF), like a standard IF (36 MHz or 44 MHz), a low IF (4-4.5 Mhz) or a zero IF. This also requires different signal processing hardware blocks based on the IF type. Hence additional area and power would have been incurred if multiple tuners catering to various standards have to be supported on the same chip.
Further, DTV and ATV systems found in the market today are extremely inflexible. They cannot support field upgradeability, additional support of a non-implemented standard, or even support a new feature for an existing standard without mandating a device redesign. With more new DTV standards evolving today, such platforms would need to be redesigned from scratch, due to which a market opportunity window would be lost. There have been attempts made to address these requirements individually. One such approach to address the issue of demodulators interfacing to multiple types of tuners (e.g. standard IF, low IF and zero IF) is to build DSP hardware which is standard specific.
For interfacing to zero-IF tuners, typically two separate sampling paths obtained from an IQ ADC (Analog to Digital Converter) are required whereas for interfacing to a standard IF or a low IF tuner only one sampling path is required. Some implementations which can utilize a shared hardware for two standards can be envisioned, but they are not capable of handling more digital TV standards (ATSC, DVB-T, DVB-S, J.83A.J.83B, J.83C, ISDB-T, CDMB-T) and analog TV standards (NSTC, SECAM and PAL). One such architecture tries to perform symbol processing tasks on a DSP processor and signal conditioning stages like filtering and spectrum shaping in beginning stages within an optimized hardware accelerator. However, due to this, it is impossible for the architecture to interface to different tuners with differing intermediate frequencies.
In addition, a requirement for supporting different intermediate frequencies (e.g., 4.5 MHz, 36 MHz, and 44 MHz) and different types of tuners (e.g., a CAN tuner, a silicon tuner) requires multiple hardware signal processing chains working in parallel. Such a solution would inevitably be area expensive thus increasing cost of the demodulator. FIG. 1 illustrates a typical Advanced Television Systems Committee (ATSC) demodulation signal chain 100. The ATSC demodulation signal chain 100 includes (i) a Numerically Controlled Oscillator (NCO) 102, (ii) a pilot frequency estimation stage 104, (iii) an adjacent channel filter 106, (iv) an upsampling filter 108, (v) a sample rate convertor & matched filter 110, (vi) a band extraction stage 112, (vii) a sampling frequency offset estimation stage 114, (viii) a carrier recovery stage 116, (ix) a pilot removal stage 118, (x) a segment sync & frame sync detection stage 120, (xi) a Least Mean Square (LMS) equalizer 122, (xii) an inner deinterleaver stage 124, (xiii) a trellis decoding stage 126, (xiv) an outer deinterleaver 128, and (xv) a Reed-Solomon (RS) decoder & de-randomizer stage 130.
FIG. 2 illustrates a typical cable demodulation (J.83A and J.83C) signal chain 200. The cable demodulation (J.83A and J.83C) signal chain 200 includes a Numerically-Controlled Oscillator (NCO) 202, a down-sampling filter 204, an adjacent channel filter 206, an upsampling filter 208, an interpolation filter 210, a timing recovery stage 212, a coarse carrier recovery stage 214, a Least Mean Square (LMS) equalizer 216, a de-mapper 218, a frame sync detection stage 220, an outer deinterleaver 222, and a Reed-Solomon (RS) decoder & de-randomizer stage 224.
FIG. 3 illustrates a typical cable demodulation (J.83B) chain 300. The cable demodulation (J.83B) chain 300 includes a Numerically Controlled Oscillator (NCO) 302, a down-sampling filter 304, an adjacent channel filter 306, an upsampling filter 308, an interpolation filter 310, a timing recovery stage 312, a coarse carrier recovery stage 314, a Least Mean Square (LMS) equalizer 316, a trellis decoding stage 318, a frame sync detection stage 320, an outer deinterleaver 322, and a Reed-Solomon (RS) decoder & de-randomizer 324.
FIG. 4A illustrates a typical Digital Video Broadcasting—Terrestrial (DVB-T) demodulator chain 400A that includes a Numerically Controlled Oscillator (NCO) 402, an IF to baseband conversion stage 404, a downsampling filter 406, an adjacent channel filter 408, an interpolation filter 410, a time domain synchronization stage 412, a Fast Fourier Transform (FFT) stage 414, a frequency domain synchronization stage 416, a pilot processing stage 418, a channel estimation stage 420, a fine symbol synchronization stage 422, a frame sync detection stage 424, a channel correction and de-mapper stage 426, a bit deinterleaver stage 428, a viterbi decoding stage 430, an outer deinterleaver 432, and a Reed-Solomon (RS) decoder & de-randomizer stage 434.
FIG. 4B illustrates a typical Digital Video Broadcasting-Satellite (DVB-S) demodulation chain 400B that includes a numerically-controlled oscillator (NCO) 402, a down-sampling filter 406, an adjacent channel filter 408, an upsampling filter 436, an interpolation filter 410, a timing recovery stage 438, a coarse carrier recovery stage 440, a data selection & discard stage 442, an inner deinterleaver stage 444, a trellis decoding stage 446, a frame sync detection stage 424, an outer deinterleaver 432, and a Reed-Solomon (RS) decoder & de-randomizer stage 434.
FIG. 5 illustrates a typical Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) demodulator chain 500 that includes (i) a Numerically Controlled Oscillator (NCO) 502, (ii) an IF to baseband conversion stage 504, (iii) a down-sampling filter 506, (iv) an adjacent channel filter 508, (v) an interpolation filter 510, (vi) a time domain synchronization stage 512, (vii) a Fast Fourier Transform (FFT) stage 514, (viii) a frequency domain synchronization stage 516, (ix) a Transmission and Multiplexing Configuration Control (TMCC) decoding stage 518, (x) a frequency and time domain deinterleaver 520, (xi) a channel estimation stage 522, (xii) a hierarchical multiplexer stage 524, (xiii) a channel correction and de-mapper stage 526, (xiv) a bit deinterleaver stage 528, (xv) a viterbi decoding stage 530, (xvi) an outer deinterleaver stage 532, and (xvii) a Reed-Solomon (RS) decoder & de-randomizer stage 534.
FIG. 6 illustrates a typical analog TV signal demodulation chain 600 for the analog TV standards Phase Alternating Line (PAL), National Television System Committee (NTSC) or Sequential Couleur Avec Memoire (SECAM). The analog TV signal demodulation chain 600 includes (i) a Numerically Controlled Oscillator (NCO) 602, (ii) a carrier recovery stage 604, (iii) an image rejection and down sampler stage 606, (iv) an adjacent channel nyquist filter 608, (v) a video low pass filter 610, (vi) a group delay equalization filter 612, (vii) a DC and gain adjust stage 614, (viii) an upsampling filter 616A, (viii) an upsampling filter 616B, and (ix) an audio band pass filter 618. The signal chains of FIGS. 1 to 6 are typically implemented either using hardwired architectures, general purpose DSPs or Application specific Signal processors (ASSP).
Hardwired architectures are ideally suited for implementing standard specific demodulation. However they are not flexible and cannot be reused as they are more expensive. The hardwired architecture does not scale with addition of new features or standards. Receivers perform complex signal processing algorithms that need to be adaptive. Any minor changes force an expensive silicon re-spin. Further, as the number of standards to be supported increases, hardwired architectures need more ‘silicon real estate’. This results in higher recurring costs. In addition, moving hardware implementation blocks across product lines is difficult and expensive. A general purpose programmable DSP like the TI C6x can be an alternative to the hardwired architectures. However a general purpose DSP is targeted for a wide range of applications like MPEG decoding, graphics and others. This leads to a solution that is prohibitively expensive for consumer applications.
The hardwired architectures and general purpose DSPs are two ends of the spectrum. The benefits of both a hardwired architecture and a DSP can be met by an architecture based on Application Specific Signal Processors (ASSP). These ASSPs are designed specifically to solve a class of signal processing problems in an application.
FIG. 7 illustrates a cost 702 versus flexibility 704 a curve 700 for different architectures such as an ASIC, a GPP (General Purpose Processor), a DSP (Digital Signal Processor), and an ASSP (Application specific Signal processor). The cost versus flexibility curve 700 illustrates that ASSPs are characterized by maximum flexibility at lowest cost.
An alternative implementation of a demodulator can be envisioned by integrating standard specific demodulators with separate paths in their receive signal processing chains. This could start from Intermediate Frequency (IF) processing which is done at sample rate, and end with demapping which is performed at a symbol rate, just before an inner and an outer decoding is performed. However such a demodulator that is constructed by integrating standard specific demodulators would be area and cost expensive, and would also consume significantly more power. It is extremely difficult to create a reusable-shared hardwired architecture to cater to all digital and analog TV standards due to a multitude of reasons. One such reason is that the sampling rate of IF signals obtained in various TV standards required for receiving them with minimum adjacent channel interference is different for each of the standards. The frequencies may range from 25 MHz to 80 MHz.
In addition, for zero IF tuners, there is additional processing required for IQ imbalance correction, which is absent in standard and low-IF tuners. Hence, it is impossible to supporting all types of tuners for several Intermediate frequencies (IF) using shared resources, since several replicas of hardware for IF processing tuned to respective standards are required. Further, some standards are based on a single carrier (e.g. ATSC, single carrier mode of CDMB-T, NTSC, PAL and SECAM) while some others like DVB-T, DVB-S, ISDB-T, multicarrier mode of CDMB-T are based on multi-carrier modulation techniques like OFDM. While demodulation of multicarrier standards is typically done using block based techniques, single carrier standards cannot be treated in a similar way. This typically leads to two different philosophies of hardware design which are impossible to merge and thereby support on a shared signal processing hardware.
Further, carrier and timing recovery methods used for different digital TV and analog TV standards differ because for single carrier standards (e.g., ATSC) there is a suppressed pilot or analog TV standards which have colour and sound carriers. For Multi-carrier standards (like DVB-T, DVB-S, ISDB-T, CDMB-T etc) the received signal consists of multiple tones. For Cable standards (ITU-T J.83A/J.83B and J.83C) the transmitted signal is pilot-less. Thus the carrier/timing recovery scheme required for supporting multiple TV standards on a single chip would require different signal processing hardware. This inevitably leads to a much larger area and increased cost. For instance, a Television (TV) communication standard is considered as an example. Further, other communication standards include a 3G standard, a Wi-Fi standard, a LTE standard, a Bluetooth standard, or any other such standards are also having same drawbacks discussed in the TV standards.
Equalization methods used across different standards to overcome multipath environments are also radically different. While most of the multi-carrier (OFDM) based standards estimate channel impulse response using frequency domain analysis (like FFT) or a combination of time and frequency domain analysis, most of the single-carrier based standards require a time domain equalizer with variable feed-forward and feedback taps. Again such a huge difference makes it impossible to share the same resource in a hardware based implementation. Thus supporting multiple communication standards would need disparate hardware to be integrated thereby increasing area significantly.